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preliminary 0.1 12/11 copyright ? 2011 by silicon laboratories SI52142 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. SI52142 pci-e xpress g en 1, g en 2 & g en 3 c lock t wo o utput g enerator with 25 mh z r eference c lock features applications description the SI52142 is a spread-controlled pc ie clock generator that can source two pcie clocks and a 25 mhz reference clock. the device has three hardware output enable control inputs for enabling the respective outputs on the fly while powered on along with the hardware input for spread spectrum and frequency control on outputs. in addition to the hardware control pins, i 2 c programmability is also ava ilable to promptly achieve optimum clock signal integrity through skew and edge rate control on true, compliment, or both differential outputs as well as amplitude control. functional block diagram ? pci-express gen 1, gen 2 & gen 3 compliant ? low power push-pull type differential output buffers ? integrated resistors on differential clocks ? dedicated output enable hardware pin for each clock ? hardware select able spread control ? two pci-express clocks ? 25 mhz reference clock ? 25 mhz crystal input or clock input ? i 2 c support with readback capabilities ? triangular spread spectrum profile for maximum electromagnetic interference (emi) reduction ? industrial temperature ?40 to 85 o c ? 3.3 v power supply ? 24-pin qfn package ? network attached storage ? multi-function printer ? wireless access point ? routers control ram control & memory xin/clkin xout sclk sdata ss [1:0] oe [1:0] diff0 diff1 ref pll1 (ssc) oe_ref divider patents pending ordering information: see page 18 pin assignments vdd_ref ref oe_ref 1 vss_ref vdd_diff oe_diff0 1 vss_core xin/clkin xout 1 2 3 4 5 6 24 23 22 21 20 19 7 8 9 10 11 12 18 17 16 15 14 13 ss0 2 ss1 2 nc nc nc vdd_diff vdd_core sdata sclk oe_diff1 1 vdd_diff diff1 diff1 diff0 diff0 notes: 1. internal 100 kohm pull-up. 2. internal 100 kohm pull-down. 25 gnd
SI52142 2 preliminary 0.1
SI52142 preliminary 0.1 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. crystal recommendatio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. oe clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.3. oe assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.4. oe deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5. ss[1:0] clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. test and measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.1. serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2. data protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. pin descriptions: 24-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
SI52142 4 preliminary 0.1 1. electrical specifications table 1. dc electrical specifications parameter symbol test condition min typ max unit 3.3 v operating voltage vdd core 3.3 5% 3.135 3.3 3.465 v 3.3 v input high voltage v ih control input pins 2.0 ? v dd + 0.3 v 3.3 v input low voltage v il control input pins v ss ? 0.3 ?0.8v input high voltage v ihi2c sdata, sclk 2.2 ? ? v input low voltage v ili2c sdata, sclk ? ? 1.0 v input high leakage current i ih except internal pull-down resistors, 0 < v in < v dd ?? 5 ? a input low leakage current i il except internal pull-up resis- tors, 0 < v in < v dd ?5 ? ? ? a 3.3 v output high voltage (se) v oh i oh = ?1 ma 2.4 ? ? v 3.3 v output low voltage (se) v ol i ol = 1 ma ? ? 0.4 v high-impedance output current i oz ?10 ? 10 a input pin capacitance c in 1.5 ? 5 pf output pin capacitance c out ?6pf pin inductance l in ?? 7 nh dynamic supply current i dd_3.3v all outputs enabled. differ- ential clocks with 5? traces and 2 pf load. ?? 40ma
SI52142 preliminary 0.1 5 table 2. ac electrical specifications parameter symbol condition min typ max unit crystal long-term accuracy l acc measured at vdd/2 differential ? ? 250 ppm clock input clkin duty cycle t dc measured at vdd/2 47 ? 53 % clkin rise and fall times t r /t f measured between 0.2 v dd and 0.8 v dd 0.5 ? 4.0 v/ns clkin cycle to cycle jitter t ccj measured at vdd/2 ? ? 250 ps clkin long term jitter t ltj measured at vdd/2 ? ? 350 ps input high voltage v ih xin/clkin pin 2 ? vdd+0.3 v input low voltage v il xin/clkin pin ? ? 0.8 v input high current i ih xin/clkin pin, vin = vdd ? ? 35 a input low current i il xin/clkin pin, 0 < vin <0.8 ?35 ? ? a diff at 0.7 v diff duty cycle t dc measured at 0 v differential 45 ? 55 % any diff clock skew from the earliest bank to the latest bank t skew(win dow) measured at 0 v differential ? ? 50 ps diff cycle to cycle jitter t ccj measured at 0 v differential ? 35 50 ps output pcie gen1 refclk phase jitter rms gen1 includes pll bw 1.5?22 mhz, = 0.54, td=10 ns, ftrk=1.5 mhz with ber = 1e-12 040 108ps output pcie gen2 refclk phase jitter rms gen2 includes pll bw 8?16 mhz, jitter peaking = 3 db, = 0.54, td=12 ns, low band, f < 1.5 mhz 02 3.0ps output pcie gen2 refclk phase jitter rms gen2 includes pll bw 8?16 mhz, jitter peaking = 3 db, = 0.54, td=12 ns, high band, 1.5 mhz < f < nyquist 02 3.1ps output phase jitter impact? pcie gen3 rms gen3 includes pll bw 2 ? 4 mhz, cdr = 10 mhz) 00.5 1.0ps diff long term accuracy l acc measured at 0 v differential ? ? 100 ppm diff rising/falling slew rate t r / t f measured differentially from 150 mv 1? 8v/ns voltage high v high ?? 1.15v voltage low v low ?0.3 ? ? v crossing point voltage at 0.7 v swing v ox 300 ? 550 mv
SI52142 6 preliminary 0.1 ref(25 mhz) at 3.3 v duty cycle t dc measurement at 1.5 v 45 ? 55 % rising and falling edge rate t r / t f measured between 0.8 and 2.0 v 1.0 ? 4.0 v/ns cycle to cycle jitter t ccj measurement at 1.5 v ? ? 300 ps long term accuracy l acc measured at 1.5 v ? ? 100 ppm enable/disable and set-up clock stabilization from power-up t stable ?? 1.8ms stopclock set-up time t ss 10.0 ? ? ns table 3. absolute maximum conditions parameter symbol condition min typ max unit main supply voltage v dd_3.3v functional ? ? 4.6 v input voltage v in relative to v ss ?0.5 ? 4.6 v dc temperature, storage t s non-functional ?65 ? 150 c temperature, operating ambient t a functional ?40 ? 85 c temperature, junction t j functional ? ? 150 c dissipation, junction to case ? jc jedec (jesd 51) ? ? 35 c/w dissipation, junction to ambient ? ja jedec (jesd 51) ? ? 37 c/w esd protection (human body model) esd hbm jedec (jesd 22-a114) 2000 ? ? v flammability rating ul-94 ul (class) v?0 moisture sensitivity le vel msl jedec (j-std-020) 2 note: while using multiple power supplies, the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required . table 2. ac electrical specifications (continued) parameter symbol condition min typ max unit
SI52142 preliminary 0.1 7 2. functional description 2.1. crystal recommendations the clock device requires a parallel resonance crystal. substituting a series resonance crystal causes the clock device to operate at the wrong freque ncy and violates the ppm specification. for most applications there is a 300 ppm frequency shift between series and parallel crystals due to incorrect loading. 2.1.1. crystal loading crystal loading plays a critical role in achieving low ppm performance. to realize low ppm performance, use the total capacitance the crystal sees to calcul ate the appropriate capacitive loading (cl). figure 1 shows a typical crystal configuration using the two tr im capacitors. it is import ant that the trim capacitors are in series with the crystal. it is not true that load capacitors are in parallel with the crystal and are approximately equal to the load capacitance of the crystal. figure 1. crystal capacitive clarification 2.1.2. calculating load capacitors in addition to the standard external trim capacitors, consider the trace capacitance and pin capacitance to calculate the crystal loading correctly. again, the capacitance on each side is in series with the crystal. the total capacitance on both side is twice the specified cr ystal load capacitance (cl). trim capacitors are calculated to provide equal capacitive loading on both sides. figure 2. crystal loading example table 4. crystal recommendations frequency (fund) cut loading load cap shunt cap (max) motional (max) tolerance (max) stability (max) aging (max) 25 mhz at parallel 12?15 pf 5 pf 0.016 pf 35 ppm 30 ppm 5 ppm
SI52142 8 preliminary 0.1 use the following formulas to calculate the trim capacitor values for ce1 and ce2. ?? cl: crystal load capacitance ?? cle: actual loading seen by crystal using standard value trim capacitors ?? ce: external trim capacitors ?? cs: stray capacitance (terraced) ?? ci : internal capacitance (lead frame, bond wires, etc.) 2.2. oe clarification the oe pins are active high inputs used to enable and disa ble the output clocks. to enable the output clock, the oe pin needs to be logic high and the i 2 c output enable bit needs to be logic high. there are two methods to disable the output clocks: the oe is pulled to a logic low, or the i 2 c enable bit is set to a logic low. the oe pins is required to be driven at all time and even though it has an internally 100 k ? resistor. 2.3. oe assertion the oe signals are active high input used for synchronous stopping and starti ng the output clocks respectively while the rest of the clock generator continues to function. the assertion of the oe signal by making it logic high causes stopped respective output clocks to resume normal opera tion. no short or stretched clock pulses are produced when the clock resumes. the maximum latency fr om the assertion to active outputs is no more than two to six output clock cycles. 2.4. oe deassertion when the oe pin is deasserted by making its logic low, the corresponding output clocks are stopped cleanly, and the final output state is driven low. 2.5. ss[1:0] clarification ss[1:0] are active inputs used to se lect differential output frequency and enable spread of ?0.5% on all diff outputs as per table 5. table 5. ss0 and ss1 frequency/spread selection ss1 ss0 differential frequency differential spread configuration 0 0 100 mhz spread off default 0 1 100 mhz ?0.50% 1 0 125 mhz spread off 1 1 200 mhz spread off load capacitance (each side) total capacitance (as seen by the crystal) ce = 2 x cl ? (cs + ci) ce1 + cs1 + ci1 1 + ce2 + cs2 + ci2 1 () 1 = cle
SI52142 preliminary 0.1 9 3. test and measurement setup this diagram shows the test load configuration for the differential clock signals. figure 3. 0.7 v differential load configuration figure 4. differential measurement for differential output signals (for ac parameters measurement) measurement point 2pf 50 ? measurement point 2pf 50 ? l1 l1 = 5" out+ out- l1
SI52142 10 preliminary 0.1 figure 5. single-ended measurement for differential output signals (for ac parameters measurement) figure 6. single-ended clocks with single load configuration figure 7. single-ended output signal (for ac parameter measurement) v min = ?0.30v v min = ?0.30v measurement point 4 pf 50 ? se clocks l 1 l 2 l1 = 0.5", l2 = 5" ? 33
SI52142 preliminary 0.1 11 4. control registers 4.1. serial data interface to enhance the flexibility and function of the clock synthe sizer, a two-signal serial interface is provided. through the serial data interface, various devi ce functions, such as individual clo ck output buffers are individually enabled or disabled. the registers associated with the serial data interface initializ e to their default setting at power-up. the use of this interface is optional. clock device register changes are normally made at system initialization, if any are required. the interface can not be used during system operation for power mana gement functions. 4.2. data protocol the clock driver serial protocol accepts byte write, by te read, block write, and block read operations from the controller. for block write/read operation, access the by tes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any comp lete byte is transferred. for byte write and byte read operations, the system controller can acce ss individually indexed bytes. the of fset of the indexed byte is encoded in the command code described in table 1 on page 4. the block write and block read protocol is outlined in table 6 while table 7 outlines byte write and byte read protocol. the slave receiver address is 11010110 (d6h). table 6. block read and block write protocol block write protocol block read protocol bit description bit description 1 start 1 start 8:2 slave address?7 bits 8:2 slave address?7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code?8 bits 18:11 command code?8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 byte count?8 bits 20 repeat start 28 acknowledge from slave 27:21 slave address?7 bits 36:29 data byte 1?8 bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 45:38 data byte 2?8 bits 37:30 byte count from slave?8 bits 46 acknowledge from slave 38 acknowledge .... data byte /slave acknowledges 46:39 data byte 1 from slave?8 bits .... data byte n?8 bits 47 acknowledge .... acknowledge from slave 55:48 data byte 2 from slave?8 bits .... stop 56 acknowledge .... data bytes from slave/acknowledge .... data byte n from slave?8 bits .... not acknowledge .... stop
SI52142 12 preliminary 0.1 table 7. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1start 1start 8:2 slave address?7 bits 8:2 slave address?7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code?8 bits 18:11 command code?8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 data byte?8 bits 20 repeated start 28 acknowledge from slave 27:21 slave address?7 bits 29 stop 28 read 29 acknowledge from slave 37:30 data from slave?8 bits 38 not acknowledge 39 stop
SI52142 preliminary 0.1 13 reset settings = 00000100 reset settings = 00000000 control register 0. byte 0 bitd7d6d5d4d3d2d1d0 name ref_oe type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7:3 reserved 2ref_oe output enable for ref. 0: output disabled. 1: output enabled. 1:0 reserved control register 1. byte 1 bitd7d6d5d4d3d2d1d0 name type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7:0 reserved
SI52142 14 preliminary 0.1 reset settings = 11000000 reset settings = 00001000 reset settings = 00000110 control register 2. byte 2 bitd7d6d5d4d3d2d1d0 name diff0_oe diff1_oe type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 diff0_oe output enable for diff0. 0: output disabled. 1: output enabled. 6 diff1_oe output enable for diff1. 0: output disabled. 1: output enabled. 5:0 reserved control register 3. byte 3 bitd7d6d5d4d3d2d1d0 name rev code[3:0] vendor id[3:0] type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7:4 rev code[3:0] program revision code. 3:0 vendor id[3:0] vendor identification code. control register 4. byte 4 bitd7d6d5d4d3d2d1d0 name bc[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7:0 bc[7:0] byte count register.
SI52142 preliminary 0.1 15 reset settings = 11011000 control register 5. byte 5 bit d7 d6 d5 d4 d3d2d1d0 name diff_amp_sel diff_amp_cntl[2] dif f_amp_cntl[1] dif f_amp_cntl[0] type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 diff_amp_sel amplitude control for diff differential outputs. 0: differential outputs with default amplitude. 1: differential outputs amplitude is set by byte 5[6:4]. 6 diff_amp_cntl[2] diff differential outputs amplitude adjustment. 000: 300 mv 001: 400 mv 010: 500 mv 011: 600 mv 100: 700 mv 101: 800 mv 110: 900 mv 111: 1000 mv 5 diff_amp_cntl[1] 4 diff_amp_cntl[0] 3:0 reserved
SI52142 16 preliminary 0.1 5. pin descriptions: 24-pin qfn table 8. SI52142 24-pin qfn descriptions pin # name type description 1vdd_ref pwr 3.3 v power supply 2ref o, se 3.3 v, 25 mhz crystal reference clock 3oe_ref i,pu 3.3 v input to disable ref clock (internal 100 k ? pull-up). refer to table 1 on page 4 for oe specifications. 4vss_ref gnd ground 5oe_diff0 i,pu 3.3 v input to disable diff0 (internal 100 k ? pull-up). refer to table 1 on page 4 for oe specifications. 6 vdd_diff pwr 3.3 v power supply 7ss0 i, pd 3.3 v tolerant latch-input for enabling frequency/ spread selection on diff0 and diff1 outputs. refer to table 1 on page 4 for ss[1:0] speci- fications. 8ss1 i, pd 9nc nc no connect 10 nc nc no connect vdd_ref ref oe_ref 1 vss_ref vdd_diff oe_diff0 1 vss_core xin/clkin xout 1 2 3 4 5 6 24 23 22 21 20 19 7 8 9 10 11 12 18 17 16 15 14 13 ss0 2 ss1 2 nc nc nc vdd_diff vdd_core sdata sclk oe_diff1 1 vdd_diff diff1 diff1 diff0 diff0 notes: 1. internal 100 kohm pull-up. 2. internal 100 kohm pull-down. 25 gnd
SI52142 preliminary 0.1 17 11 nc nc no connect 12 vdd_diff pwr 3.3 v power supply 13 diff0 o, dif 0.7 v, 100 mhz differential clock 14 diff0 o, dif 0.7 v, 100 mhz differential clock 15 diff1 o, dif 0.7 v, 100 mhz differential clock 16 diff1 o, dif 0.7 v, 100 mhz differential clock 17 vdd_diff pwr 3.3 v power supply 18 oe_diff1 i,pu 3.3 v input to disable diff1 (internal 100 k ? pull-up). refer to table 1 on page 4 for oe specifications. 19 sclk i smbus compatible sclock 20 sdata i/o smbus compatible sdata 21 vdd_core pwr 3.3 v power supply 22 xout o 25.00 mhz crystal output, float xout if using only clkin (clock input) 23 xin/clkin i 25.00 mhz crystal input or 3.3 v, 25 mhz clock input 24 vss_core gnd ground 25 gnd gnd ground for bottom pad of the ic table 8. SI52142 24-pin qfn descriptions (continued) pin # name type description
SI52142 18 preliminary 0.1 6. ordering guide part number package type temperature lead-free SI52142-a01agm 24-pin qfn industrial, ?40 to 85 ? c SI52142-a01agmr 24-pin qfn?tape and reel industrial, ?40 to 85 ? c
SI52142 preliminary 0.1 19 7. package outline figure 8 illustrates the package details fo r the SI52142. table 9 lists the valu es for the dimensions shown in the illustration. figure 8. 24-pin quad flat no lead (qfn) package table 9. package diagram dimensions symbol millimeters min nom max a 0.70 0.75 0.80 a1 0.00 0.025 0.05 b 0.20 0.25 0.30 d 4.00 bsc d2 2.60 2.70 2.80 e 0.50 bsc e 4.00 bsc e2 2.60 2.70 2.80 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.07 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline mo-220, variation vggd-8. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
SI52142 20 preliminary 0.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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